Engel, Konrad 1956- VerfasserIn aut Kalinowski, Thomas 1980- VerfasserIn aut Labahn, Roger 1959- VerfasserIn aut Sill, Frank VerfasserIn aut Timmermann, Dirk 1957- VerfasserIn aut text Text gw 2005 monographic XA-DE Rostock University of Rostock, Institute of Mathematics publisher 2005 Rostock Universitätsbibliothek distributor eng

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1 Online-Ressource (19 Seiten) In this paper, we consider an optimization problem on directed acyclic graphs which is motivated by a standard task in low power VLSI design. With each vertex v of a directed acyclic graph, we associate two delay values d0(v) ≤ d1(v) and two leakage values c0(v) ≥ c1(v). The objective is to choose one of the indices 0 or 1 for each vertex, such that in first instance the corresponding total delay along any directed path is minimal, and in second instance the total leakage is minimized. We prove that a very restricted special case of this problem already is NP-hard, and we present four different heuristic approaches to the problem. Further, we test our algorithms on ISCAS85 benchmark circuits.<eng> Open Access Urheberrechtsschutz 1.0 Konrad Engel, Thomas Kalinowski, Roger Labahn, Frank Sill, Dirk Timmermann 510 https://purl.uni-rostock.de/rosdok/id00005895 Rostock : Univ., Fachbereich Mathematik, 2005

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